Cache Aware Data Layouts

Malik Silva
Department of Statistics and Computer Science
University of Colombo and Department of Scientific Computing
Uppsala University


Feeding the processor with data operands is the bottleneck in many scientific computations. This bottleneck is alleviated by means of caches, small fast memories to keep data. The performance of a memory-intensive computation depends critically on whether most of the data accesses can be performed within the cache. This research is on cache aware computing, in which the programmers make their code cache friendly. In particular, we have tested cache aware data laying which is a promising technique as it gives significant performance improvements. For example, we recorded improvements of around 42% for red-black Gauss-Seidel and about 64\% for standard matrix multiplication.

Key words: memory barrier, caches, iterative algorithms, cache-aware algorithms, data layouts

AMS subject classification: 65N55, 65F10, 65-04